| 微电子科学与工程
数字集成电路课程设计课程教学大纲
Course Outline
课程基本信息(Course Information) |
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课程代码 (Course Code) |
MR322 |
*学时 (Credit Hours) |
48 |
*学分 (Credits) |
3 |
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(Course Title) |
(中文)数字集成电路课程设计 |
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(英文)Curriculum design for digital integrated circuit |
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*课程性质 (Course Type) |
面向数字集成电路设计的动手实践课 |
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授课对象 (Target Audience) |
微电子科学与工程专业(本科生)大学三年级/四年级本科生 |
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*授课语言 (Language of Instruction) |
中文/英文 |
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*开课院系 (School) |
微纳电子系 |
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先修课程 (Prerequisite) |
数字电路设计、数字集成电路设计、微电子概论、Verilog HDL电路设计 |
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授课教师 (Instructor) |
何卫锋 |
课程网址 (Course Webpage) |
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*课程简介(Description) |
集成电路产业是我国战略性新兴技术产业。数字集成电路课程设计面向集成电路产业前沿的应用需求和先进芯片设计技术,重点培养学生从事超大规模集成电路硬件架构设计、集成电路的结构级建模、基于先进EDA工具链的芯片设计和实现能力。 高性能视频编码(High efficiency video coding,简称HEVC) 是 MPEG和ITU组织面向未来超清视频应用(Ultra High Definition TV,简称UHDTV)而联合开发的新一代视频编码标准。课程设计将基于新一代的HEVC视频编码标准,重点研讨满足不同应用需求的IDCT电路/ME电路的硬件结构设计、IDCT/ME电路的RTL建模与功能仿真、IDCT/ME电路的逻辑综合与时序分析、IDCT/ME电路的物理综合与芯片版图设计等内容。通过本课程设计,学生要初步学会使用主流EDA前端和后端工具独立从事数字和系统芯片的设计开发工作。
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*课程简介(Description) |
IC industry is of one of strategic and emerging industries in China. Based on cutting-edge IC applications and advanced chip design technologies, The Curriculum design of digital integrated circuit design is focused on ability training on VLSI hardware architecture design, RTL modeling for Integrated Circuit, chip design and layout implementation with advanced EDA tools. High efficiency video coding (HEVC) standard is the emerging video coding standard which is jointly developed by the MPEG and ITU for the future ultra-High Video applications (Ultra High Definition, UHD). Based on the HEVC standard, IDCT or ME hardware architecture design for different applications, IDCT/ME circuit modeling and RTL functional simulation, logic synthesis and IDCT/ME circuit timing analysis, physical synthesis and IDCT/ME chip design are major contents of the curriculum. After the course, students may have the ability to design a real IC chip independently by using the current popular front-end and back-end EDA tools.
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课程教学大纲(course syllabus) |
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*学习目标(Learning Outcomes) |
1.了解和掌握HEVC视频编码标准中的IDCT/ME算法的基本原理 2.学会进行面向不同应用需求的IDCT/ME电路的硬件结构设计 3.学会使用HDL进行IDCT/ME电路的RTL建模、testbench开发和功能仿真; 4.学会基于Synopsys Design Compiler的IDCT/ME电路的逻辑综合方法、综合脚本准备与时序分析; 5.学会基于Synopsys IC Compiler/Cadence Encounter的IDCT/ME电路的物理实现方法、综合脚本准备与时序分析;
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*教学内容、进度安排及要求 (Class Schedule &Requirements) |
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*考核方式 (Grading) |
(成绩构成)课程的成绩包括平时成绩、中期成绩和设计报告成绩,三部分成绩所占的比率为45:30:25 |
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*教材或参考资料 (Textbooks & Other Materials) |
1. Verilog HDL Coding Semiconductor Reuse Standard, Motorola 2. HDL Compiler for Verilog User Guide, Synopsys 3. 精通Verilog HDL:IC设计核心技术实例详解,电子工业出版社 4. 数字逻辑设计-第四版,人民邮电出版社 5. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE 6. IC Compiler workshop, Synopsys 7. Design Compiler Workshop, Synopsys 8. Prime Time Workshop, Synopsys |
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其它 (More) |
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备注 (Notes) |
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备注说明:
1.带*内容为必填项。
2.课程简介字数为300-500字;课程大纲以表述清楚教学安排为宜,字数不限。